Multiplicador em corpo finito utilizando redes neurais discretas.

Abstract

Finite body calculations are widely used in code correction errors, digital signal processing, pseudorandom number generation, and schematics of encryption. Generally these modern applications require implementations that meet the high speed requirements. Assuming the polynomial representation of body elements, addition and simple to implement while rapid parallel multiplication requires a more complex structure. Other important arithmetic operations of finite bodies, such as exponentiation and division, can be performed by repeated multiplications. Consequently, efficient multipliers are desired since most advanced arithmetic operations are based on multiplication. Discrete neural networks implemented with linear threshold ports allow to reduce the complexity of certain circuits previously implemented with traditional logic (AND, OR and NOT ports). Much research has been done regarding the application of linear threshold gates in basic arithmetic operations (addition, multiplication and division). These operations can be implemented with linear threshold gates using a low gate number and fixed delay. The idea of ​​extending the use of linear threshold gates in basic arithmetic operations for finite body arithmetic is proposed in this paper. This dissertation presents a parallel GF (2n) multiplier architecture based on the Mastrovito multiplier with linear threshold gates. Also a new architecture and proposal, more efficient in terms of temporal and spatial complexity and keeping a low spatial complexity.