Associação em paralelo de conversores estáticos com barramento CC.

Abstract

The present work deals with the parallel connected AC-DC-AC converters used for low and medium power application, in order to increase reliability, performance and quality of the power conversion systems. In this context, nine parallel connected AC-DC-AC converter configurations have been investigated, which fall into three categories: (i) single-phase to single-phase converter, (ii) single-phase to three-phase converter, and (iii) three-phase to three-phase converter. Among these configurations, six are formed by direct parallel connection of two AC-DC-AC converters, two configurations for each category. Two other topologies in the single-phase to single-phase category are proposed. These topologies are based on two AC-DC-AC shared-leg converters. The last proposed topology belongs to the single-phase three-phase category. It is composed of two parallel single-phase converters and one three-phase converter. In order to compare the investigated topologies, the following criterias are considered: (a) harmonic distortions analysis in the voltage and current waveforms, (b) the power losses caused by the high frequency component through the dc-link, (c) semiconductor switching and conduction losses. For harmonic distortions, the equivalent inductor size and switching frequency influences on the grid current are considered. Dynamic modelling of the configurations are developed, including the circulating-current modelling. The generalization of topologies are also derived. The control system provides high power factor, current sharing among the parallel converters and minimization of circulating-current. In the case of PWM strategies, the impacts of using apportioning factor and multi carrier-based PWM on the system performance are investigated. The configurations studied in this work presented better performance than the conventional one under same operating conditions. Finally, simulation and experimental results are presented and compared in order to validate the proposed topologies.