Circuito integrado para multiplicação em GF (24) utilizando portas de limiar linear.

Abstract

This dissertation describes the development of a layout of new multiplication architecture in Galois field based on the Mastrovito multiplier. The processing unit of this new architecture is a threshold logic gate, which is a basic element of a discrete neural network. The discrete neural network built with threshold logic gates allow reduce de complexity of a certain circuits once built using traditional boolean gates (AND, OR and NOT). Therewith, the idea of extending the advantages of the threshold logic gates for arithmetic operations in Galois field to become very attractive. Thus, to confirm into practice form, the advantages of the threshold logic gates, a multiplier architecture in GF(24), proposed in (LIDIANO - 2000), was implemented using the integrated circuit layout tools of Mentor Graphics®. The results from simulations of the layout of multiplier in GF(24) are presented. These results indicated a low performance, due to the space complexity of GF(2n) multiplier with n = 4 is not enough for show the advantages of the multiplier implementation with threshold logic gates.