Análise da área de operação segura e estudo da robustez do transistor MOSFET de carbeto de silício.

Abstract

This work was developed at the same time as the developemment of a power module for aircrafts applications in Laboratory IPES in Lyon, France. The main object is to evaluate the robustness of the gate oxide of the semiconductors wide-gap components, particularly SIC MOSFET marketed since 2011. Indeed the silicon Carbide present many advantages compared to silicon including a lower specific resistance reducing conduction losses. The use of SiC MOSFET has become very interesting in rail or aviation applications. This study start by making a state of the art on theMOSFET safety area defined conventionally by the on-state limit, the breakdown voltage limit or avalanche phenomenon, the current or short circuit limit and thermal limit defined by the maximum power. An improvement in the safety area is proposed later and a new safety area defined by a boundary timepower. Finally prediction of the limits to protect our component allows us to address the robustness of the gate oxide.