Desenvolvimento de um gerador de modelos de referência para compiladores de memória.

Abstract

Memories are one of the densest electronic circuits in respect to the number of transistors per unit area. The reliability of new circuits has been a very important point for designers of integrated circuits. Therefore, they plan to deal with a wider sort of simulations to be executed during the phase of design of this device. One of these sorts of simulations uses reference models written in Verilog to analyze the circuit logic. Nowadays, the design flow of ARM memory compilers has some weaknesses. Among those weaknesses, it will be treated here the absence of a complete functional verification and the level of complexity to modify the current Verilog reference models. The main goal of this internship is to propose a different way of writing Verilog reference models, suppressing those weaknesses. This internship also aims to find an alternative software to the ESP-CV due to internal affairs faced by the company. Firstly, a concept of a simple model was made to evaluate the viability of this sort of model. A reference model generator for the same architecture was afterward developed and its advantages and disadvantages evaluated. Thereafter, the same proceedings were made to a different architecture. Therefore, a better evaluation for this new methodology was acquired through a more detailed study. Finally, the purpose of a new design flow has brought the possibility to reach the main targets. Although a substitute for the ESP-CV was not found, the Conformal was used to formally verify the digital circuits. The analog ones continue being verified by the same software.