Conversor analógico-digital assíncrono.

Abstract

The aim of this thesis is contribute in the category of integrated complex circuits systems development, the main objective is to present the design of a clockless analog-todigital converter, with the features of low-power consumption and low-complexity. For this, it was defined the project of an asynchronous analog-to-digital converter, with an irregular sampling process, the “crossing levels sampling”, that is a non-uniform sampling in the time. This thesis presents an 8 bits clockless analog-to-digital converter project, based on a folding architecture. The first part of the work is based on the converter project in the CMOS 0,35 μm technology standard, with a supply voltage of 3,3 V. The simulation results of this 8 bits converter presented a Signal-to-Noise and Distortion Ratio (SNDR) of 58 dB, with a power consumption of 35 mW. The proposed converter circuit was also compared by simulations, with a similar pipeline converter, operating in continuous time, with 8 bits, and 1 bit per stage, designed with the same technology standard, and obtained a SNDR of 50 dB. The second part of the work was the circuit layout conception and validation, based on simulations from the designed layout for the SNDR projected value and the desired power consumption. The main applications for an asynchronous converter are those where the activity of the analog signal is not constant during all the conversion period. In this work was focused the application of this type of converter in spectrometry of gamma rays, in which the events occur randomly with Poissonian distribution.