Contribuição ao estudo de identificação e compensação de faltas em inversor multinível com diodos grampeadores.

Abstract

This paper presents a contribution to the study of detection, identification, and compensation of faults in diode-clamped three-level inverters. First, the study of existing multilevel inverter topologies is done, emphasizing their advantages, disadvantages, and implementation difficulties. Next, a more detailed study of the diodeclamped three-level inverter is achieved. An investigation of the inverter under open and short-circuited conditions allows for the presentation of the resulting post-fault configurations and of their vector diagrams, as well. Since the detection and identification of the switches short-circuit fault can be accomplished by command, more emphasis has been given to the analysis of the open switch fault case. An extensive simulation analysis shows that the fault detection, and finding in which phase the failure occurred, can be achieved as for conventional two-level inverters: by detection of either the pole voltage error (difference between reference and measured values) or its propagation to the line and common-mode voltages together with a proposed strategy to locate which specific switch in the phase leg is under fault. In all cases the scalar pulse width modulation strategy has been used. Finally, a comparative study of topologies that are able to compensate both types of faults (open circuit and short-circuit) establishes their post-fault limitations and operation possibilities together with modifications in the modulation strategy. The viability of the theoretical proposals is verified by simulation and experimental results.