Análise de cobertura funcional na fase de integração de blocos de circuitos digitais.

Abstract

One of the biggest challenges in a digital circuit design is to assure that the final product complies with its specifications. Functional verification is a widely employed technique to certify that the digital circuit design complies with its specifications. Due to complexity of digital circuits, the engineers create hierarchical designs, breaking a complex block into simpler blocks. Hence, the functional verification is performed in accordance with the hierarchical decomposition for the design. However, the composition phase is not well treated by the functional verification methodologies. They do not determine how to proceed in a systematic way to reduce integration time and explore new scenarios that may arise from the interaction between blocks. This work presents a functional verification approach that is specific for the design blocks composition phase. This approach is able to promote the reuse of verification components, the preservation of the coverage criteria of the blocks, the exploitation of new scenarios emerging from the interaction of blocks and time reduction in functional verification. The experiments in this work provided significant improvements in digital circuit designs that were developed in the academic domain. By means of structural coverage metrics, it was shown that the new specification of functional coverage can exercise pieces of code that had not been exercised up to the time of integration.