Utilização de aritmética bit-serial para redução de consumo de energia.

Abstract

Today, one of the biggest concerns, if not the largest, for the semiconductor industry is the development of chips with low power consumption. There are several physical phenomena that cause power consumption in CMOS circuits and various techniques that reduce the energy consumption of a chip. The main objective of this masters research was to investigate how the static power consumption in CMOS circuits can be reduced through the use of bit-serial arithmetic in place of bit-parallel arithmetic. The research is focused on circuits built from standard cells, with application to signal processing, and for which the main requirement is not the high computing performance, but the low power consumption. The methodology was applied in a case study, using for this, simulations with the SPVR IP core. The SPVR is a vocal identity checker implemented in a dedicated circuit able to have enough performance to run in real time, even employing a slow clock signal. It has been found in research that the use of bit-serial arithmetic, in terms of reduction of static consumption, is advantageous to adders and small circuit complexity. However, for more complex systems, this substitution is only advantageous in specific situations of large number of arithmetic operations and low storage usage in parallel registers. In the reverse case, the advantages are lost, because although there are static consumption decrease, there is a very large dynamic consumption growth.