BRUNELLI, L.; http://lattes.cnpq.br/8019874133102405; BRUNELLI, Luiz.
Resumen:
In this thesis a new solution for the treatment of the complexity in the interconnections
among the processing elements of the artificial neural networks (ANNs) is
described. It enables realize ANNs digital hardware implementation with a larger number
of neurons than does nowadays. The ANNs have been used as a solution in various
complex problems. Some of these problems require hardware implementation. A lot of
constraints must be satisfied during the project flow of the implementations of ANNs,
such as the neural interconnections. Nowadays, neural implementations are done using
integrated circuits, specifically developed for a given neural network architecture or
integrated circuits configured by the user. Among these circuits exist the dynamically
reconfigured FPGAs (DR-FPGAs) which can have their characteristics changed during
operation without suffering interruptions in their execution. These devices have been
usedforANNimplementations. Itpresentsaproposaltosolvethe interconnection problem
for artificial neurons using DR-FPGAs in a new computational way: the Execution
Patterns1 (EPs). The EPs allow, theoretically, to reduce the influence of interconnections
through the removal of data transport via busses, besides other advantages and
disadvantages. TheEPsdoesnotseemtoberestrictedonlytoANNapplications. They
can be used by reconfigurable computation in massive parallel problems and/or problems
that demand information exchange among the various elements in a processing
system.