GOMES, L. V.; http://lattes.cnpq.br/9663603094783048; GOMES, Luana de Vasconcelos.
Resumo:
The performances of the next generations of CMOS integrated circuits (technology 45
nm then 32 nm even 22 nm) will be mainly limited by the electric performances of the
networks of interconnections. These interconnections introduce in a combined way some
problems of delay and crosstalk during the transmission of the signals, and all the more than
the density of integration of the components increases. Integration in three dimensions (3D) is
a solution planned to limit the inconvenience associated to the traditional interconnections. It
is under these conditions to achieve a stacking of multiple chips interconnected surface
reduced it by vias. One of the other innovative solutions proposed to answer these problems
consists in the wireless interconnections radio frequency (RF).
This study consists to use integrated antennas to establish a wireless transmission inter
chip in 3D stacking, and is focused mainly on the transmission of clock signals.