Arquitetura e implementação em hardware de um módulo MFCC para extração de características da voz.

Abstract

Techniques of digital Processing of Speech Signals are being used in Speaker Recognition Systems. Howevwr, in the focus of this study, it was approached the technique of mel-cepstral coefficients (MFCC), and the hardware implementation of a logarithm, which is part of the features extraction from speech system that was acomplished here. Simulations were performed for comsumption and area occupied on the chip. Consumption reduction tecniques have been studied and applied in ordr to eliminate the use of multipliers by employing Egyptian multiplication, that performs sums and bit shift operations.