Ambiente de verificação funcional de um IP-core em UVM.

Abstract

Functional Verification is a major stage in dedicated digital integrated circuits design, also known as IP-Core, avoiding implementation mistakes and flaws to reach the physical design and the final client as well, compromising the correct functionalities of the component. UVM is a methodology composed by a library of SystemVerilog classes that allow a transaction level modeling environment test, making possible it’s reuse in many IP’s. Once being a well-established and largely used methodology such in industrial design as academic environments, it was described in a systematic way a verification environment implementation procedures in UVM for a generic IP, demonstrating it’s fuctionality.