Verificação formal para hardware.

Abstract

The formal verification has great importance in the business world of technology, due to the increase in the complexity of hardware and software systems which has led to a greater number of fail found in the projects. That is why the use of formal verification is becoming more and more present in the market, this is due to optimization of time of production that this method provides, thus generating less expenses during the confection of the products. Because of this, there is a perceived need to train more and more verification teams in formal methods, and it is necessary to create more documentation that will assist verifiers in the use of formal logic. Having this problem in mind, this work was developed to serve as a practical guide for a verifier to be able to perform a formal verification on a hardware, making use of the SystemVerilog Assertions language in conjunction with an open source environment that makes use of UVM, the SVAUnit.