Ferramenta para análise de confiabilidade em circuitos digitais.

Abstract

Currently, with the increase of the complexity of digital circuits and the decreasing size of transistor, the digital circuits are more susceptible to faults. To obtain more practicality in estimatation, precisely, of the reliability of them, due to critical circuits (circuits that compose systems that it‘s fault put lives in risk), thereby, It’s is described in this present document a tool and an analysis form, given that, with a given circuit netlist is possible to evaluate the realiability of the circuit. The tool was developed part with SystemVerilog and part with Python.