Sistema de emulação para arquiteturas RISC-V.

Abstract

The development of central processing units is job with great hardships. From the conception phase to the hardware implementation. It requires knowledge of several digital systems structures and how they interact with each other. Besides that, the transition betwen conception phase and implementation phase surface several unpredictible changes due to functional limitations, that on most cases are only identifiable through practical functional analysis. Aiming to be a transition point and reference module to those architecture , an emulation system was developed to offer, ahead of time, practical tests, functional debug and logic dubug. All the architecture developed and studied throughout this project uses RISCV-V as their instruction set. The choice was made due to the open source characteristic.