Implementação de gerador de Testbench UVM.

Abstract

Inserted in a restrict time-to-market environment, the microelectronics area is constantly challenged to deliver devices in this limited dedlines. This fact is even stronger for the verification sector, which usually accounts for 70% of the project duration. In this context, the UVM testbench generator is developed as an automation tool to help engineers on both IP verification kickoff and to account for design modifications.