Implementação em hardware de um algoritmo de transformada rápida inteira de Fourier para aplicações de baixa potência.

Abstract

The Discrete Fourier Transform is one of the most fundamental operations presents in digital signal processing chips today, with a growing need for faster, smaller, low-power devices. In this sense, this work aims to develop the front end of an Integer Fourier Fast Transform block using power-aware techniques. To this end, Soontorn Oraintara’s work on the Integer Fast Fourier Transform (IntFFT), the fundamentals of the discrete-time Fourier transform of Allan V. Oppenheim, and the Fast Fourier Transform algorithms implementation of Uwe Meyer-Baese. The methodology used follows the ASIC (Application Specific Intregrated Circuits) development flow encompassing the specification, modeling, digital circuit design and logic synthesis steps. As a result, it was possible to obtain a netlist from the logical synthesis of a 8 point IntFFT, using the split-radix algorithm being reported the area, power and performance of the referred block. The proposed design can be adapted and used to generate larger transforms due to its architectural decisions of portability and reuse.