Nova arquitetura de multiplicador em GF (28) utilizando portas de limiar linear.

Abstract

This dissertation describes the design, the developing and the implementation in hardware of a new architecture of multiplying finite fields based upon the Mastrovito multiplier. Such architecture utilizes linear threshold ports as basic processing elements, which are the basic elements of a discrete neural network. The discrete neural networks implemented with threshold ports allow reduce the complexity of the circuits when they are compared to implementations of traditional logics (AND, OR and NOT ports). For this reason, extending and implementing linear threshold ports in the arithmetic’s of the finite fields becomes an attractive activity. Thus, with the objective of proving the efficiency of such ports as basic units of processing of the multiplying architecture in GF (2n), that it has been designed, in the hardware description language Verilog, a GF (28)multiplier utilizing the linear threshold ports. Several levees of abstraction have been developed. The FPGA (Field-Programmable Gate Array) Quartus II® tool and the developing Altera® hardware EP2C35F672C6 have been utilized. The results of the development which are presented indicate the practical functioning of the new architecture proposed by the GF (28) multiplier. However, its efficiency in terms of time processing and counting of ports is under what would be expected. From the results the multiplication operation in finite fields was observed with an accuracy rate of 90%.