Verificação funcional distribuída para projetos de circuitos integrados baseados em arquiteturas heterogêneas.

Abstract

This work deals with the functional verification of hardware designs based on heterogeneous architectures. One method is designed to reduce design time by excluding and adapting steps from the conventional design flow. These changes aim to use legacy IP-cores through the use of an integration interface of heterogeneous architectures. The testbench of the pro posed functional verification method is based on the SystemC library and uses the concept of Virtual Bus from the High-Level Architecture (HLA) specification. Thus, the integration of an IP core requires the development of a communication wrapper with testbench. The proposed testbench was used to verify the design of a system composed of two subsystems, one that converts RGB to YCbCr (S1) and another that calculates the integral of the image (S2). Two verification scenarios were considered. In the first the two subsystems are con nected in series, and in the second, they are connected in parallel. In the first scenario, the IP cores of S1 and S2 were made available in C++/OpenCL and SystemVerilog, respectively. In the second scenario, the IP cores of S1 and S2 were made available in OpenCL and SystemVerilog, respectively. In these two scenarios, the public domain IP-cores were used, and the respective external communication wrappers were implemented. The “golden models” of these IP colors were considered to be available. In the first scenario, the testbench was used to integrate the available implementations using Virtual Bus, being necessary to implement specific wrappers for C++/OpenCL and SystemVerilog in the scope of the testbench. In the second verification scenario, the testbench was used to integrate the available implementations using Virtual Bus, being necessary to implement specific wrappers for OpenCL and C++ with SystemVerilog, in the scope of the testbench. Tests are applied in usage scenarios with 10, 000 samples generated from an image. The serial scenario compares the output generated from S1 to S2 with a golden model. The parallel scenario compares the generated outputs of S1 and S2 with golden models. Therefore, the method reduced design time without recoding, adding steps to the design flow.