Uma arquitetura autotestável para circuitos digitais baseada no algoritmo de Berlk Amp-Massey e em sistemas imunológicos artificiais.

Abstract

Currently, the cost of testing an integrated circuit is estimated at approximately 25% of the total cost of its production and it is predicted that by 2015 this cost will reach 50%. This cost is directly related to the costs of using automatic test equipment. Such equipment is extremely expensive and with the advancement in integrated circuit manufacturing technology and the increased operation speed of these circuits are becoming inaccurate in the detection of faulty circuits. A very promising alternative in reducing theses costs and developing self-testing integrated circuits that are rapidly becoming a widely used test technique used in the industry for testing VLSI circuits. The main components in these self-testable architectures are the test generators and the response analyzers that perform the generation of tests and the analysis of the circuit responses to these theses in the circuit itself to those tests in the integrated circuit itself, respectively. The main objective of this thesis is to present a complete scheme of an autotestable architecture proposing a noco scheme of a test generator and an answer analyzer. The proposed test generator is based primarily on the Berlekamp-Massey algorithm and on a genetic algorithm-based optimization process. This generator is totally based on the architecture of a Linear Feedback Shift Register (LFSR) and is capable of generating both deterministic tests, which detect the circuit's difficult detection failures, and tests pseudo-random, which detect the remaining faults. With regard to the proposed response analyzer, a scheme based on the human immune system is proposed. In the design of this scheme is used the negative selection algorithm inspired by this system. Such a negative selection process gives the body the ability to discriminate between its own cells and cells foreign to it. From this inspiration, a response analyzer capable of detecting whether or not the first circuit is faulted or not is proposed. Using the development methods of the test generator and the proposed response analyzer, some simulation results, which demonstrate the method efficiencies, are shown using the ISCAS85 and ISCAS89 performance verification circuits.