Uma metodologia de verificação funcional para circuitos digitais.

Abstract

The advent of new VLSI technology and SoC design methodologies, has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any design flow. New methods are required that allow for easier, quicker and more reusable verification. In this work is proposed a novel functional verification methodology to digital components, which follows the project flow, allowing the testbench (simulation environment) to be generated before the Design Under verification implementation. In this way, the functional verification process become faster and the verification engineer can trust in the testbench, because it is verified before the DUV´s functional verificationDUV.