Aplicação do RISC-V formal verification framework para verificação formal de um núcleo de processamento.

Abstract

Hardware verification is essential to ensure the quality of electronic circuits. In this context, formal verification is capable of finding bugs that would be too hard to find in a dynamic simulation, boosting verification quality. Based on properties, formal verification attempts to prove that a design shows the intended behaviors and does not show undesired behaviors. The RISC-V Formal Verification Framework is an open-source formal verification tool, which enables the verification of processing cores based on RISC-V architecture. We therefore proposed to apply this tool on the CV32E40P processor used in the PULP platform, which is also open-source. With that, we were able to find bugs in the design and understand why they happened.