REVOREDO, M. L. M.; REVOREDO, Maria Luceneide Mota.
Resumen:
This project consists of the design and construction of an 8 - channel Logic Analyzer, with timing diagram out outford is play on a conventional laboratory o scilloscope. lt accepts either TTL or CMOS input, and has a memory of 2048 bits .
The purpose of this Analyzer is the testing of digital sisterns. It has a trigger word, user selected, to serve as a reference state in t his testing.