Relatório de estágio integrado no Laboratório de Excelência em Microeletrônica do Nordeste-XMEN.

Abstract

This report presents the work carried out during the integrated internship at the Excelên cia em Microeletrônica do Nordeste (XMEN) Lab, focusing on the formal and functional verification of processor cores based on the RISC-V architecture. Using the RISC-V Formal Verification Framework (RFVF), tests were conducted on the CV32E40P core, coninuing a previously done work with a different version of the core, now carrying out consistency and Xcorev extension tests. In parallel, the internship included the develop ment of the RISC-X processor, also based on RISC-V, where verification was carried out through a UVM testbench and Risc-V Formal.