Desenvolvimento de um gerador de banco de registradores em hardware.

Abstract

This work presents the development of an automated tool for generating register banks in hardware (SystemVerilog) using Python. The tool aims to reduce the development time of ASICs and minimize manual errors. The project implements AMBA APB as the communication protocol, ensuring flexibility and adaptability to different architectures. The results show that the proposed solution is effective in improving the productivity and quality of hardware designs, while also offering potential for future expansions.