Design e verificação funcional de um bloco I2C controller.

Abstract

This work aims to develop a digital design and functional verification of an I2C controller, a crucial component in data communication for embedded systems. The I2C protocol is widely used in the electronics industry for interconnecting integrated devices, and the controller plays the role of the main controller in this bus. The objective of this project is to design and verify an I2C controller block, considering hardware and/or software aspects such as architecture definition, communication interface, control logic, and basic read and write operation modes. Functional verification is a crucial step to ensure the correct functioning of the I2C controller block, and tests will be developed to verify its behavior in a communication scenario defined by the presence of only one target and the transmission of one data per transaction in normal mode. The project will also address the digital design development of the I2C controller block, which will operate under the mentioned conditions, taking into account the specifications provided by NXP Semiconductors©

. Functional verification and digital design will be implemented using the hardware description language SystemVerilog. To ensure the block’s functionality, synthesis and verification environment simulation were performed using the following software: Cadence© Xcelium Logic SimulatorTM, Cadence© Genus Synthesis SolutionTM, Cadence© Simvision WaveformTM, and Cadence©

Integrated Metrics CenterTM.