CAVALCANTE, J. H. F.; CAVALCANTE, José Homero Feitosa.
Résumé:
A TABLE DRIVEN SIMULATOR IS DEVELOPED FOR
SIMULATION OF LOGIC SYSTEMS, ON THE DIGITAL COMPUTER. A SIMPLE
MODEL FOR THE LOGIC BLOCKS BASED ON PROPAGATION DELAY AND
OUTPUT AMBIGUITY DURING SWITCHING IS USED. THE SIMULATOR
ENABLES DETECTION OF HAZARDS AND CRITICAL RACES IN THE
COMBINATORIAL AND SEQUENTIAL CIRCUITS RESPECTIVELY.
A METHOD FOR SIMULATION OF SYSTEM DESCRIBED
BY BOOLEAN EQUATIONS IS INDICATED AND A TECHNIQUE FOR
OBTAINING COMPUTER GENERATED DRAWINGS OF THESE SYSTEMS IS
SUGGESTED.