SAMPAIO, R. B.; http://lattes.cnpq.br/1715941386400515; SAMPAIO, Ricardo Brandão.
Resumen:
In this work we describes all the necessary stages to the development of design a
Core of Intellectual Property (IP SoftCore) and how to elaborate your functional
validation, also we describe all the necessary platforms for the elaboration of each
stage of the project. That design Core has for function perform the conversion play of
the interface of PCI local bus, of width of 32 bits and frequency 33 MHz, for a the
interface whose the bus does use of the protocol OCP-IP™ of same width and
frequency of the interface of PCI bus. For development of the Interface was
necessary to elaborate a PCI Target unit and an unit OCP™ Master. The design of
IP SoftCore was totally accomplished in the Hardware Description Language
SystemC™, as well as the test environment for simulation and the device application
of the user. The implementation of the Core was especially developed to adapt itself
for device reconfiguration as FPGA FLEX 10KE of the company Altera that it was
used in prototype stage. The results obtained in simulation environment were
satisfactory, at the end of the project had itself answers for setup and cycles reading
and writing cycles of reading and writing in the memory. The implementation stage
was incomplete, only the setup environment was implemented in FPGA (reading and
writing cycles in the setup configuration space).