Geração semiautomática de testbenches para circuitos integrados digitais.

Abstract

Functional verification complexity tends to increase exponentially with design size. The Moore’s law places an ever growing demand on today’s verification engineer to continue to ensure that no bug is missed in the verification process. The time necessary and money spent on the verification process increases the demand because it consumes most of the resources of a hardware project. Thus, an approach that has a flexible tool and helps the verification engineer in his tasks can be very useful in the verification process. The verification methodology VeriSC can help to solve several problems involving funcional verification. This work’s objective is a supporting tool for VeriSC methodology useful for automated construction of simulation environments (Testbenches) enabling a flexible way to speed up verification tasks.