Projeto e análise de uma chave bootstrapped para redução de não linearidades em circuitos de amostragem.

Abstract

This work presents the design and analysis of a bootstrapped sampling switch aimed at reducing non-linearities in sample-and-hold circuits applied to analog-to-digital conversion systems. The main objective is to improve the linearity and accuracy of the sampling process by employing the bootstrapping technique proposed by Abo and Gray, which maintains the switch gate-to-source voltage (VGS) nearly constant during the sampling phase, regardless of variations in the input signal. The project was developed using a 180 nm CMOS technology, with simulations performed in the Cadence Virtuoso environment. The methodology involved circuit validation through DC and transient simulations, as well as the analysis of performance metrics such as SNDR, SNR, and ENOB. The results indicate a significant improvement in the linearity and performance of the sampling circuit when compared to a conventional switch, highlighting the benefits of the bootstrapping technique in reducing distortion and improving sampling quality.